1. Field of the Invention
The present invention relates to semiconductor device technologies and engineering, and more particularly to the technologies of the protection of semiconductor devices from process-induced charging damages during semiconductor device processing.
2. Description of the Related Art
The antenna effect or the floating gate effect is the name given to the phenomena of induced voltages that can collect on partially processed leads. The effect is partially prevalent during plasma processes e.g., etching, deposition, ashing and ion implantation, and can lead to damage to thin gate oxide regions of the device under construction.
Process-induced charging and ensuing gate oxide damage constitutes a significant yield and reliability detriment for submicron CMOS technology. Problems occur at many stages of processing, but are aggravated by long lead lengths at lead definition following the material of the lead deposition, and the material of the lead can be, polysilicon, copper and aluminum, for example. As devices are further scaled to reduced geometries, the gate oxide becomes progressively thinner and hence more susceptible to damage, even at reduced voltages.
Charge accumulation on partially processed leads, and the resultant voltage increase, can cause voltage overstress and result in charge trapping in gate oxides and gate oxide breakdown. Previously, simple n+/p or p+/n junction diodes were used to protect oxides from the antenna effect during VLSI processing. As gate oxides have become thinner in reduced geometry devices, such as 0.5 micron and further reduced geometry devices, gate oxide damage tends to occur prior to protective junction diode breakdown. As a consequence, use of the diode for protection from the antenna effect discussed above becomes ineffective as the gate oxide thickness is scaled below thicknesses of about 100 angstroms, which have breakdown voltages on the order of about 16 volts or less. Accordingly, it would be desirable to provide an alternative type of protective device that is operable to protect gate oxides having thicknesses below about 100 angstroms, as can be expected to be required in the generation ULSI (i.e., less than 100 angstroms gate oxide thickness) and further reduced geometry devices.
FIG. 1A depicts a conventional protection device 10 used to solve the charge induced antenna effect, and FIG. 1B shows the circuit. It is to be appreciated that the illustrated device can be constructed in accordance with a variety of known processing techniques, the specific manner of processing not being relevant to the following discussion. The protection device 10 includes a substrate 12 that is typically formed from a semiconductive material such as silicon, which is doped with a p-type impurity. The semiconductor substrate 12 can also be formed from a variety of other semiconductive materials, such as GaAs and HgCdTe, for which the principles of the present invention that are set forth below are likewise applicable. In the illustrated structure, a metal oxide semiconductor field effect transistor (MOSFET) under construction is designated generally by reference character 14, and the associated protective component, is designated generally by reference character 16. The protective component that is presently utilized in the art is typically an n+/p or a p+n junction diode.
The protection device 10 includes shallow trench isolation (STI) regions 18a-18d, which can be developed in the substrate 12 in a conventional manner. Interposed between the STI regions 18a and 18b are source and drain regions 26a, 26b that is formed by using conventional methods, and a gate oxide region 22 that is typically thermally grown to a thickness of about 4-20 nm. A layer of polysilicon 24 is patterned and applied in an appropriate manner over the gate oxide 22 and doped with an appropriate impurity, such as phosphorus, to render the polysilicon layer 24 conductive. Dielectric layer 32 is applied over the polysilicon and underlying STI regions 18a-18d and is patterned and etched to create a channel such as a contact opening that extends from an upper surface of the dielectric layer 32 to an upper surface of the polysilicon layer 24 and a channel that extends from an upper surface of the dielectric layer 32 to a moat region 36. The contact opening can be filled with an appropriate metal conductor, such as an alloy of aluminum or copper, to establish electrical contact between non-adjacent levels of the protection device 10.
The illustrated junction diode 16 includes the moat region 36 which is typically doped with an n+ impurity to produce an n+/p junction diode. The junction diode 16 is electrically connected to the device gate oxide 22 by a metal lead line 34, thereby permitting the junction diode to preferentially leak electric current from the gate oxide region 22 and thereby protect the gate oxide 22 from currents that may pass through the device. However, in such manner, a protection diode would need to be designed into the integrated circuit for each transistor to insure protection.
This approach set forth is wasteful of die area because the introduction of these diodes that include diffusion areas occupy additional area of the integrated circuit. For example, in certain designs, the use of diodes can occupy 30%-40% of the area of the die. Moreover, the introduction of these additional diffusion areas, by virtue of the layout rules, takes up additional area in addition to the actual diffusion area to meet these minimum distance requirements of the layout rule. Therefore, this approach wastes die area, increases the cost of the integrated circuit, and sacrifices transistor density. Accordingly, a semiconductor device for protecting the gate electrode of transistors in a die that save more diffusion area as compared with the conventional one that use the protection diodes, and that reduces the cost and space consumption is desired.
It is therefore an object of the invention to provide a semiconductor device for preventing the process-induced charging damages by sharing cumulative charges with parasitic capacitors of the invention used as energy pools.
It is another object of this invention to provide a semiconductor device for protecting devices from the process-induced charging damages, and fighting against charges build up on the gate oxide of the protected devices by leading the majority of cumulative charges to the parasitic capacitors.
It is a further object of this invention to provide a semiconductor device for protecting devices from the process-induced charging damages, meanwhile, saving more chip area than the conventional one by virtue of the use of the parasitic capacitors.
It is also an object of this invention to compensate potential chemical mechanical polishing (CMP) dishing problems by using a dummy conductive layer constituting a dummy pattern as one electrode of the parasitic capacitor.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a semiconductor device comprising a semiconductor layer, at least one transistor comprising a source region, a drain region, a channel region, a gate oxide layer and a gate electrode, at least one parasitic capacitor comprising a conductive layers, a dummy conductive layer constituting a dummy pattern, and a dielectric layer interposed individually between the conductive layer and the dummy conductive layer, a first conductor connecting the gate electrode and the conductive layer, and a second conductor connecting the semiconductor layer and the dummy conductive layer. Furthermore, the dummy conductive layer can be a floating layer over the semiconductor layer. In such manner, the second conductor set forth is replaced by an interposed dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.